(Editor's Note: In
Part 1 of this tutorial, the author discussed the limitations of
traditional simulation techniques as a means of specifying high speed
hardware interfaces and the benefits of shifting to a methodology based
on PCB design procedures.)
High speed printed circuit board (PCB) design involves the tasks of
controlling:
1) Flight Time Delay and Skew
2) Signal Integrity and
Impedance Matching
3) Crosstalk
4) Power Supply Bypassing
5) EMI
In the classical high speed flow, timing specifications and
simulation modeling are performed to determine constraints required for
the tasks listed above. In this case, the silicon manufacturer has
evaluated the simulations and timing specifications. The task at hand
here is to communicate rules for the listed tasks directly to an
arbitrary PCB designer. The next sections describe the ways the items
listed above can be constrained by generic PCB rules.
| This article is excerpted from a paper of
the same name presented at
the Embedded Systems Conference Boston 2006. Used with permission of
the Embedded Systems Conference. For more information, please visit www.embedded.com/esc/boston/ |
Flight Delay and Skew
The fundamental high speed PCB issue is flight time delay and skews.
The overall constraint for this is the placement of the components. The
maximum placement refers the placement in which the distances between
the devices are the furthest permitted.
Controlling the maximum placement of devices combined with the
assumption that good practices are followed will limit maximum trace
delay to about the longest Manhattan distance of the signals contained
in a clock domain.
The reason it will be the longest Manhattan distance is due to skew
matching requirements: all of the shorter nets in a clock domain must
be lengthened to skew match to the longest one. Thus, flight time delay
and flight time delay skew are controlled by the maximum placement.
Signal Integrity and Impedance
Matching
Signal integrity in this context refers to controlling overshoot, ring
back, and transition edges. As shown in the previous section, the
placement controls the maximum trace lengths. Given a constrained
length, one can control signal integrity by controlling the PCB trace
topology of the various parts of an interface. Included in this
topology are any terminations. It is quite possible to make these
terminations optional.
Terminations are a dual edged sword. In one case they are very
effective at controlling overshoot which leads to better crosstalk and
EMI performance. On the other hand, they also raise bill of materials
(BOM) parts count and they consume sizable PCB real estate. If in the
end, a non-terminated design passes signal integrity, crosstalk, and
EMI requirements, then one can argue they were never required in the
first place. If the termination is optional the design should pass
signal integrity and cross talk requirements without terminators.
The problem is EMI. Leaving terminations off a design will increase
risk of failing EMI emission requirements. This is discussed further
below in the EMI section. Effective signal integrity control on high
speed designs requires that the impedance of the PCB traces themselves
be controlled.
Trace impedance is governed by the trace width as well as the
thickness and dielectric constant of the PCB insulating material
(usually FR- 4). Fortunately for the PCB designer, this aspect can
often be left to the PCB fabrication contractor by simply specifying
the desired single ended impedance for the PCB traces.
Differential impedance can also be handled this way, but
implementation is a little trickier because the spacing between the
differential traces influences differential impedance as well. Proper
differential impedance is ensured via cooperation between the PCB
layout designer and the PCB fabrication contractor.
Thus, signal integrity is controlled by the allowed PCB signal trace
topology. Termination schemes are considered part of that topology.
Indirectly, stackup and trace widths control signal integrity as well
by controlling impedance mismatch.
Crosstalk
Crosstalk is fundamentally controlled by the PCB stackup and minimum
trace spacing. While improvements have been made, good crosstalk
simulation can be quite difficult. The best approach to avoiding a
crosstalk problem is to ensure the signals all have high quality signal
return paths and to spread the signal traces out.
One must not forget the rudimentary concept key to electrical
current flow: It flows in a loop. Sometimes this simple concept is lost
because there is usually only once signal trace " the return path is
"hidden" in a ground plane in a solidly designed PCB. System schematics
also hide this loop by frequent use of the "ground" symbol. The larger
the area inside the loop the better the loop is at propagating signal
energy to its surroundings " namely other signals and the environment
around the PCB.
It is well known that return currents prefer to flow directly
underneath the signal trace in a ground plane4. This path results in
the smallest loop. If there is no ground plane, the return current will
attempt to find another path.
The current will also deviate within a ground plane if it encounters
a cut in the plane. Return currents can also flow in a power plane, but
this path is longer as well because at some point the current must jump
to a true ground point via a bypass capacitor. Larger loops result in
more crosstalk and more electromagnetic radiation. Thus it is desirable
to keep these loops as small as possible.
Control of current return paths can be done in the PCB stackup. Each
signal routing layer should have an adjacent full ground plane to
provide the shortest return current path. Note that it is permissible
for signal layers to share a common ground plane.
The other aspect of crosstalk control is signal separation. It is
also well known that spreading signal traces out beyond the PCB minimum
spacing dramatically lowers crosstalk to the adjacent signal[5] The
minimum separation is purely a mechanical specification controlled by
the PCB technology used to manufacture the board.
The PCB technology is chosen such that the densest circuitry can be
routed (usually BGAs). Thus, some minimum spaced signal routing must
occur near the dense devices. Since the amount of coupling between two
parallel traces is also dependant on the length for which they are
parallel, it is advantageous to spread these traces out wherever
possible. Spacing them at two to three times the minimum trace spacing
results in a very sizable reduction in crosstalk.
Thus, crosstalk is controlled by the stackup which provides quality
ground return paths and trace spacing rules that spread the signals out
on the PCB. Typically, there must be a provision in the spec that
allows for the relaxation of trace spacing rules near dense component
escapes.
Power Supply Bypassing
Proper power supply bypassing is essential for a properly functioning
high speed PCB. The fundamental parameter here to control is the power
supply high frequency impedance which means controlling power supply
inductance.
Power supply high frequency impedance is beaten down by utilizing
many physically small capacitors connected between the power and ground
planes. Using many capacitors, rather than one large one, results in
their parasitic inductances being placed in parallel, thereby reduced.
The parasitic inductance of a capacitor is dependant upon its size.
The practical limit for the number of bypass capacitors is the
geography of the PCB. The bypass capacitors need to be placed very
close to the device they are bypassing. Once the semiconductor devices
are chosen, one can determine from the placement how many capacitors
will fit.
The high speed specification needs to communicate how many are
required and give guidelines for placement. It is also critical to
provide rules about how the capacitors are connected to the planes.
Wrong via choices can increase parasitic inductance significantly.
It is generally best to use the largest capacitance value easily
obtainable in the smallest package. However, differing values can help
when power supply EMI issues are created due to power supply
resonances. Fortunately, it is usually easy to tune these values after
prototypes are built during EMI testing. Adding bypass capacitance
mounting locations after PCB manufacture is almost impossible without a
PCB spin due to the inductance issue, thus placing as many as possible
is recommended.
EMI
EMI simulation can be particularly difficult, and as in crosstalk
control, it is a problem best avoided by following good high speed
design practice. EMI is also addressed in the same way as crosstalk "
good signal return paths limit loop area which limits crosstalk and
EMI.
Ringing and overshoot aggravate EMI as well as crosstalk. Ringing in
high speed systems occurs at the natural frequency of the system. These
higher frequencies can propagate more easily. Termination that reduces
this ringing also reduces EMI, but the terminations come at a cost of
increased BOM count and PCB space.
The cost-benefit equation of EMI versus termination has different
results for different silicon customers. Laying out the benefits and
the risks of termination options and letting the designer make the
choice is a reasonable alternative. For example, leaving optional
terminations off a design may result in an EMI certification failure.
Addressing this may require adding terminations. However, a
terminator-less design will likely not have room to add the needed
components. This could mean an entire design has to be redone almost
from scratch. Thus, the trade off is a smaller, lower parts count
design versus a risk of failing EMI.
A middle of the road approach is to design with terminators and
populate them with zero ohm resistors. The design is then checked for
EMI compliance and only those terminations that are required are added
back. It is then easy to remove the zero ohm terminators in a board
spin.
Customers for which board space is at such a premium that they must
do without terminators need to place room in their schedules for board
spins in case of EMI issues.
The final component to EMI control is providing a reference design
that follows the PCB spec and passes EMI compliance testing. It is less
risky making small incremental changes from a design that is known to
pass EMI than
to design something new from scratch.
Schematics and Electrical
Connections
The purpose of the material following is an attempt to answer the
straightforward question "How do I hook it up?"
The concepts described here were developed during the design phase
of the TMS320C6455 DSP from Texas Instruments. This approach to timing
specification was used on the DDR2 and Serial RapidIO interfaces on
this device. Other interfaces on the device are supported using the
traditional method. Devices since the development of the C6455 have
also used this approach to document the requirements of their DDR2
interfaces[6].
Note that this approach is by no means limited to just DDR2. Any
high speed timing requirements can be specified this way as long as it
is bounded by a limited number of connection options. The C6455
specification was used here because it was convenient.
Electronic schematics or net
lists can be troublesome because of the sheer number of PCB CAD design
packages in use. Fortunately, schematic entry is not that demanding of
a job, especially if a "paper copy" schematic is available. The manual
entry may seem like a step backwards, but it is an effective way of
accurately importing the schematic into a wide variation of customer
design flows.
Stackup. A fundamental
specification of a PCB is its stackup. In this case it is specified as
a minimum required for the interface while using the lowest cost PCB
technology. This minimum PCB stackup is primarily derived by the
physical layer count required to escape and fully route the components
as well as appropriate reference planes to minimize crosstalk.
This stackup only accounts for the DDR2 portion of the PCB. The
system designer is free to add layers to the PCB in order to reduce the
area required by the DDR2 interface or for routing requirements of
other circuitry on the PCB.
Also included here are any impedance matching requirements for the
board. In addition, an explicit warning is given about proper ground
reference planes. This is done because the ground reference planes are
crucial to controlling crosstalk and EMI.
Placement. The placement
section of the specification tells the PCB designer the parameters for
placing the components of the interface. Placement is based upon clear
reference points on the packages. Of all the specifications, the
placement is the most dominant in controlling signal delay. Obtaining
trace delays corresponding to within 10% of the Manhattan distance is
straightforward.
The provided placement is a maximum placement. This maximum
placement allows the routing of the PCB using the lowest cost PCB
technology possible. There is no restriction on the minimum placement.
This allows the customer to determine the appropriate trade off between
PCB size and PCB technology (cost).
Also provided in the placement are the parameters for the variable
keep-out region designed to minimize cross-talk between the DDR2
interface and other PCB circuitry. The variable keep-out is determined
from the system designer's placement. This frees the design from the
constraints imposed by some fixed, arbitrary keep-out region.
All high performance semiconductors require discretes such as bypass
capacitors. They may also require other components such as EMI filters.
Bypass capacitors are given special attention due to their
importance in a successful high speed design. Minimum bypass capacitor
quantities are provided as a starting point. More importantly, rules
for connecting the bypass capacitors and power balls to the planes are
spelled out. The rules are designed to ensure the power system has low
inductance.
Discrete part placement is not fixed to allow customer flexibility.
An example discrete placement is shown. Serial terminations are
optional. If desired, recommended termination values and placement are
provided.
Crafting the PCB's physical traces
All of the sections up to this point are intended to get the system
design ready for routing. This section describes how to craft the
physical traces on the PCB that correspond to the schematic net list.
Signal Routing Rules. The
signal routing rules are used actively by the PCB designer and CAD
software. These rules are designed to control signal trace length and
skew as well as to maintain adequate spacing to control cross-talk.
Often, it is desirable to group signals that have the same
requirements into a net class. In addition, it is handy to put each
clock into its own net class as well. The signal net classes are then
associated with their clock net class. PCB CAD software uses these net
classes to apply the design rule checks for the layout. Thus, the first
step is to define these net classes so they can be used to define the
routing rules.
For maximum flexibility the routing rules are written in terms of a
variable, w, that represents the trace width. This allows the system
designer to choose an appropriate trace width. With the selection of w,
the routing rules become fixed, customized to the particular system.
Thus if a particular rule calls for 4w center to center spacing, and w
= 4 mils, the spacing becomes 16 mils. It would be 12 mils for a board
using 3 mil traces.
Net Class Routing Rules. At
this point, the devices have been chosen; the schematic netlist is
complete, the stackup has been determined, the components have been
placed, and the net classes have been defined. All that is left is to
actually define the net class routing rules.
The net class routing rules establish clear requirements on the
routing of the nets contained within. The rules are expressed in two
ways: The first is a text description of the intent for the routing for
a set of net classes. The second is done via drawings that clearly
illustrate the route length, skew, and spacing requirements.
Each routing rule set establishes the minimum trace separation that
must be maintained between signals within the associated net classes as
well as the spacing to signals in other net classes. These spacing
rules control crosstalk.
The lengths and configuration of the net topology segments are also
clearly defined. Flight time and skew delay are controlled by
controlling trace length and trace length variation.
Summary and Discussion
The alternative method for specifying high speed timing requirements
presented here has some distinct advantages over the traditional
methods:
1) The system designer does
not have to run simulations nor have access to simulation tools.
2) The silicon manufacturer
does not have to provide and support silicon models.
3) The system designer does
not have to close timing.
4) The silicon manufacturer
does not have to provide discrete timing data nor test loads.
5) The system designer knows
the PCB challenges up front.
6) The silicon manufacture
can target their device for a very specific PCB use condition.
7) The concise spec is easy
for the system designer to follow.
8) The concise spec is easy
for the silicon manufacturer to verify
Early on it was made clear that an experienced high speed designer
should be involved. In the real world, many system builders do not
posses high speed design experts or have the time for a full-up PCB
simulation and timing closure. Still, with this approach, it is
possible for a relatively inexperienced engineer to design a successful
system - all they have to do is follow the directions.
Michael Shust is a tenured design
engineer for Texas Instruments
high performance DSP product portfolio, the TMS320C6000. As a senior
applications engineer, provides expertise in troubleshooting DSP
engineering issues related to specific application areas and
understanding total system integration.
References
1) IBIS (I/O Buffer Information
Specification) Version 4.1, ANSI/EIA-656-A, January 30, 2004.
2) Michael R. Shust,
Implementing DDR2 PCB Layout on the TMS320C6455, Application Report
SPRAAA7,
Texas Instruments Inc., November 2005.
3) Todd Hiers, Implementing
Serial Rapid I/O PCB layout on a TMS320C6455 Hardware Design,
Application Report SPRAAA8,
Texas Instruments Inc., August 2005.
4) Howard W. Johnson and
Martin Graham, High-Speed Digital Design, A Handbook of Black Magic,
Upper Saddle River, NJ: Prentice Hall PTR, pp. 190-1, 1993.
5) Howard W. Johnson and
Martin Graham, High-Speed Digital Design, A Handbook of Black Magic,
Upper Saddle River, NJ: Prentice Hall PTR, pp. 191-4, 1993.
6) Michael R. Shust,
Implementing DDR2 PCB Layout on the TMS320DM644x DMSoC, Application
Report SPRAAC5,
Texas Instruments Inc., February 2006.
