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The baseband or modem processing engines in many advanced wireless systems often include a variety of programmable "off-the-shelf" signal processing devices such as digital signal processors (DSPs) and field programmable gate arrays (FPGAs).
These devices tend to evolve following some variant of Moore's law, with new generations of devices incorporating new features and capabilities introduced every two to three years.
Original equipment manufacturers (OEMs) developing advanced wireless systems can take advantage of this trend to offer their customers cost-effective feature enhancements and upgrades in existing systems through technology insertion by replacing only the baseband processing engine while retaining other subsystems, such as the RF or control subsystems as is.
This article will explore the architectural requirements necessary to facilitate this manner of technology insertion in an advanced wireless system.
Part 1 of the article will examine the requirements on the baseband processing engine hardware architecture, and propose a software/firmware model for minimizing the cost to the OEM in moving from one generation of technology to the next by maximizing the reuse of intellectual property (IP) across roadmap products.
Part 2 of the article will present a real world example illustrating the efficacy of the proposed architectural models.
Architecting the baseband processing engine for technology insertion
Baseband processing in an advanced wireless system typically provides a broad range of the radio's physical layer channel processing functions.
These include channel estimation and equalization; carrier, symbol and frame synchronization; spreading and despreading; modulation and demodulation; interleaving and deinterleaving; and channel coding and decoding for forward error correction.
As illustrated in Figure 1, OEMs typically utilize a variety of different types of signal processing technologies to provide this functionality, including application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), and general purpose processors (GPPs).
These technologies may be packaged as either discrete components or combined in system-on-chip (SoC) devices, and are interconnected to provide the data flows necessary within the baseband processing subsystem to support the target air interface standards.
Enabling future upgrades of this functionality through technology insertion requires that the baseband processing subsystem be encapsulated in a "standardized" module.
The term "standardized" in this context means having a well-defined mechanical structure or form factor that can facilitate the future replacement of the baseband processing engine and can occur while the system is in-service. It also requires well-defined interfaces between the baseband processing module and the other subsystems within the radio, including the mechanical and electrical interfaces and associated intra-system communications protocols.
With respect to this latter requirement, three well-defined primary system interfaces are typically required in a baseband processing module: the network interface, the control interface, and the RF subsystem interface.
The network interface provides support for the transport of payload data between the physical layer processing supported in the baseband processing engine and the higher level functions supported within the rest of the wireless platform.
The control interface provides support via an external control subsystem for non-real-time control of the functions within the baseband processing engine, such as starting and stopping the baseband processing and setting the mode of operation.
The RF subsystem interface provides support for the transport of digital intermediate frequency (Digital IF) signals and any associated context and control data between the analog-to-digital and digital-to-analog converter assembly in the RF front end and the first stage processing elements contained within the baseband processing module.
The context data associated with these signals may include items such as time of day and sample count that can be used to support network synchronization in the transmit and receive channels, while the control data may include time critical tuning instructions or power and bandwidth settings for the RF subsystem.
Click here for Figure 1
Figure 1: Architecture of a typical baseband processing engine utilized in an advanced wireless platform.
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