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Part 1 of this article proposed an architectural model facilitating technology insertion of intermediate frequency and baseband or modem processing engines in advanced wireless systems.
These subsystems often include a variety of programmable "off-the-shelf" signal processing devices such as digital signal processors (DSPs) and field programmable gate arrays (FPGAs) which tend to evolve following some variant of Moore's Law, with new generations of devices incorporating new features and capabilities introduced every 2 to 3 years.
Original equipment manufacturers (OEMs) developing advanced wireless systems can often take advantage of this trend to offer their customers competitive feature enhancements and upgrades of existing systems through technology insertion.
This is a cost-effective method of introducing new features by replacing only the baseband processing engine while retaining other subsystems, such as the RF or control subsystems, as is.
The model proposed for supporting this capability starts by encapsulating the baseband processing engine in a "standardized" modular architecture.
The term "standardized" in this context means having a well-defined mechanical structure or form factor that can facilitate the future replacement of the baseband processing engine while the system is in-service and having well defined interfaces between the baseband processing module and the other subsystems within the radio, including the mechanical and electrical interfaces and associated intra-system communications protocols.
The model further proposes that, in addition to "standardizing" the form factor and interfaces, support for technology insertion also requires establishing a well-defined operating environment within the baseband processing engine to facilitate reuse of the functional code supporting the physical layer processing.
The reason for such an environment in supporting technology insertion is simple: significant reductions in both cost of development and time to market can be achieved by the OEM if, for example, the DSP code in one generation of baseband processing engine can be largely reused to support the same or similar functionality in the next.
Part 2 of this article examines the proposed architecture further by exploring the efficacy of the proposed model in two real world examples " a wideband receiver platform, and a tactical military communications technology demonstrator platform.
Case study 1: Wideband receiver platform
The problem
In this case study, a radio system original equipment manufacturer (OEM) was pursuing multiple different programs where they needed the ability to monitor the spectrum over a wide frequency range and extract signals of interest for follow-on processing. The signal processing architecture of the OEM's system included three primary subsystems, as illustrated in Figure 1:
- The Spectral Analysis Subsystem, which performs a spectral analysis on the digitized wideband signal to detect potential signals of interest. This processing was primarily performed in an FPGA.
- The Channelization Subsystem, which buffers the received signal until a signal of interest is detected and then extracts signals of interest from the wideband signal and converts them to baseband for channel processing. Process to support signal extraction is performed primarily in an FPGA, whereas channel processing is primarily performed in a DSP or general purpose processor (GPP).
- The Operational Control Subsystem, which provides overall "real-time" control of the wideband receiver system while in operation.
Click here for Figure 1
Figure 1: High Level Architecture of the OEM's Wideband Receiver System.
The OEM had three key problems in developing and fielding this type of system. First, the number and types of channels required in the wideband receiver architecture varied from program to program based on each program's specific requirements.
Given the tight time constraints generally associated with their programs, the OEM needed an architecture that allowed them to easily mix and match the number and types of FPGA and DSP processors used within one system without the need to design new hardware for each program.
Secondly, the OEM planned to invest heavily in the development of the FPGA and DSP application code for their initial programs, and then reuse this intellectual property (IP) as a critical differentiator in winning future programs.
To maximize their return on investment in this IP, the system architecture had to maximize reuse of the IP from program to program.
Finally, the OEM's customers required the ability to minimize the effort, cost and disruption associated with adding enhanced features, capabilities and processing power to existing systems. Expensive forklift upgrades of the existing systems were not an option.
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