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Although 60-GHz wireless connections offer the promise of transmitting massive amounts of data over short distances using radio frequencies in part of the spectrum that are pretty much unutilized, the technical challenges of designing and building a complete transceiver in CMOS are daunting.
While CMOS is clearly the technology of choice for cost-effective fabrication, its performance at ultra-high frequencies leaves much to be desired. Power is one issue and gain is another.
Moreover, at 60 GHz, high path losses and interference created by people walking though the room and the like must be addressed. One way of doing this is by utilizing a phased antenna array approach—and this requires a programmable phase shift capability.
IMEC, the research consortium based in Leuven, Belgium, has taken an important first step in solving these problems by designing and demonstrating a 60-GHz, multiple antenna receiver in CMOS. The prototype was officially unveiled at the ISSCC meeting in San Francisco today.
IMEC's device contains two antenna paths, each consisting of a low-noise amplifier and a down-conversion mixer. A programmable phase shift is realized on the same chip. It starts from the quadrature signals of an on-chip quadrature voltage-controlled oscillator (QVCO). This QVCO design combines the highest oscillation frequency with the largest tuning range ever reported in CMOS, according to IMEC.
IMEC's multiple antenna receiver is the first step towards a complete CMOS-based phased array transceiver for 60-GHz wireless personal area networks. Applications could include multi-gigabit-per-second kiosk downloading, wireless high-definition multimedia interface (HDMI), and other applications.
Interestingly, the digital air interface has to be co-developed with the RF because designers have to live with the fact that the performance of a 60 GHz front end is not very good. For that reason, the IEEE 801.15.3 working group developing a 60-GHz standard has been evaluating modulation schemes in the context of how complimentary they will be to the RF portion of the system.
In the next phase of development, IMEC plans to implement four antenna paths using 45nm CMOS technology and to integrate other subsystems such as the phase-lock loop (PLL), analog-to-digital converter (ADC) and the patch-antenna array itself. IMEC will also begin initial experiments for a power amplifier.
These results were achieved in the unique multi-disciplinary 60GHz technology program. The research combines system-level aspects, algorithms, CMOS IC design, antenna design and module design, which target a low power 60 GHz communication link based on adaptive beamforming using multiple antennas aligned with ongoing standardization activities.
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