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Cadence Design Systems' RF Design Methodology Kit helps wireless chip designers shorten design cycles and optimize performance by integrating several point tools and establishing a reliable, proven methodology for designing transceivers in a 180nm CMOS process.
The kit includes an 802.11 b/g WLAN transceiver reference design, a full suite of RF verification IP, test plans, and applicability training on the RF design and analysis methodologies.
Although the reference design is for 802.11 b/g WLAN transceivers, in its announcment Cadence made it clear this is not an IP play but a means of demonstrating the methodology of Cadence's transceiver design flow. As such, it is useful for SoC transceivers designed to other standards such as WiMAX, UWB, Bluetooth and ZigBee.
The kit focuses on front-to-back RF IC design and addresses behavioral modeling, circuit simulation, layout, parasitic extraction and resimulation, and inductor synthesis. It also focuses on IC verification within a system context, leveraging system-level models and testbenches for use by designers in the IC environment.
The kit uses accurate 3D extraction technology and advanced physical modeling capabilities from the company's Assura RF tool. It also links to system-level environments, and offers the functionality in the the company's Virtuoso custom design platform with Flexible Balance option for calibrated results of transient and frequency analysis. The kit is not, however, tied exclusively to Cadence tools.
An example of a link to a key system-level design tool is the Virtuoso AMS Designer link to The MathWorks’ MATLAB/Simulink. This link provides an executable specification that is continually elaborated throughout the development process.
As a result, a common environment can be leveraged as IC designers verify against a system-level specification across multiple domains including system, digital, mixed-signal, and analog RF.
The announcement is the third release in Cadence's kit initiative. It was preceded by the Cadence AMS Methodology Kit and the Cadence Optimization Kit for ARM Processors. Ajay Malhotra, senior vice president of Marketing at Cadence, said the company has seen "tremendous customer interest in Cadence’s kits approach and customers can expect more Cadence kits in the near future in areas of networking and consumer electronics."
More information is available at www.cadence.com/products/kits/.
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